This invention relates to a frame synchronization circuit for use in a receiver of a digital communication system, which is typically a PCM communication system.
In a transmitter of a digital communication system, digital information signals are multiplexed into a multiplexed signal either on a word basis or on a frame basis. Usually, a frame synchronization pattern is inserted in the multiplexed signal at a frame period to have a predetermined pattern which does not appear in other parts of the multiplexed signal. In a receiver of the digital communication system, the frame synchronization pattern is detected in order to get a correct understanding of a sequential order in which the digital information signals are multiplexed. A frame synchronization circuit is for putting operation of a timing pulse generator in correct synchronism with the frame synchronization pattern.
A conventional frame synchronization circuit comprises a pattern detecting section for detecting a frame synchronization pattern in an input code sequence supplied to the pattern detecting section. Only when the frame synchronization pattern is detected, the pattern detecting section produces a pattern detection signal or pulse. Supplied with circuit input clock pulses as gate input clock pulses, a gating section allows passage of the gate input clock pulses so as to produce gate output clock pulses and inhibits passage of the gate input clock pulses so as not to produce the gate output clock pulses when controlled by first and second control signals, respectively. In compliance with the gate output clock pulses, a frame pulse generating section generates a frame pulse in each frame period. Supplied with the pattern detection signal and the frame pulse, a concurrency detecting section detects concurrency of the frame pulse with the pattern detection signal and produces the first and the second control signals when the frame pulse is and is not concurrent with the pattern detection signal, respectively.
A little more in general, the frame pulse generating section comprises a timing pulse generator and a frame pulse generator. Each gate output clock pulse is used in stepping the timing pulse generator one step. Stepped in this manner, the timing pulse generator generates various timing pulses. Based on the timing pulses, the frame pulse generator generates the frame pulse. Primarily, the timing pulses are for use in other parts of the receiver.
The frame pulse is generated at a time instant which depends on initial conditions of the timing pulse generator and the frame pulse generator. As a result, generation of the frame pulse is not necessarily concurrent with production of the pattern detection signal. The concurrency detecting section and the gating section are therefore used in adjusting the time instant of generation of the frame pulse by using the frame synchronization pattern so that the receiver may be operable in correct synchronism with the frame synchronization pattern.
It should be noted in connection with the conventional frame synchronization circuit that the pattern detection signal is used in generating the frame pulse through a loop comprising the concurrency detecting section, the gating section, the timing pulse generator, and the frame pulse generator. The loop has a loop delay, which must be shorter than one clock period of the circuit input clock pulses in order that the frame synchronization circuit is correctly operable and that the receiver is consequently correctly operable. When the circuit input clock pulses have a high clock frequency, it becomes impossible to keep the loop delay shorter than one clock period. The conventional frame synchronization circuit has therefore been inoperable depending on the circumstances.
An improved frame synchronization circuit is invented by A. Tomozawa and disclosed in Japanese Patent Publication No. 12,856 of 1975 (Syowa 50). In the manner which will later be described, the improved frame synchronization circuit is operable with no theoretical restriction on the loop delay. It should, however, be noted as regards the improved frame synchronization circuit that it becomes difficult to manufacture the pattern detecting section. This is because the pattern detecting section must be operable at a high clock frequency and becomes bulky when the frame synchronization pattern is long, namely, has a long pattern length.